Evaluation Boards - Embedded - Complex Logic (FPGA, CPLD) (301)

Surface Mount

Number of Terminals

Clock Frequency-Max

Ihs Manufacturer

Manufacturer Part Number

Operating Temperature-Max

Operating Temperature-Min

Package Body Material

Package Code

Package Description

Package Equivalence Code

Package Shape

Package Style

Part Life Cycle Code

Reflow Temperature-Max (s)

Risk Rank

Rohs Code

Supply Voltage-Max

Supply Voltage-Min

Supply Voltage-Nom

JESD-609 Code

Terminal Finish

Additional Feature

Terminal Position

Terminal Form

Peak Reflow Temperature (Cel)

Terminal Pitch

Reach Compliance Code

JESD-30 Code

Number of Outputs

Qualification Status

Power Supplies

Temperature Grade

Number of Inputs

Organization

Seated Height-Max

Programmable Logic Type

Combinatorial Delay of a CLB-Max

Number of CLBs

Number of Logic Cells

Number of Equivalent Gates

Length

Width