Evaluation Boards - Embedded - Complex Logic (FPGA, CPLD) (1)

Surface Mount

Number of Terminals

Clock Frequency-Max

Ihs Manufacturer

Manufacturer Part Number

Operating Temperature-Max

Operating Temperature-Min

Package Body Material

Package Code

Package Description

Package Equivalence Code

Package Shape

Package Style

Part Life Cycle Code

Part Package Code

Reflow Temperature-Max (s)

Risk Rank

RoHS

Rohs Code

Supply Voltage-Max

Supply Voltage-Min

Supply Voltage-Nom

JESD-609 Code

ECCN Code

Terminal Finish

HTS Code

Terminal Position

Terminal Form

Peak Reflow Temperature (Cel)

Terminal Pitch

Reach Compliance Code

Pin Count

JESD-30 Code

Qualification Status

Power Supplies

Temperature Grade

uPs/uCs/Peripheral ICs Type

Supply Current-Max

Bit Size

Seated Height-Max

Address Bus Width

Boundary Scan

Low Power Mode

External Data Bus Width

Format

Integrated Cache

RAM (words)

Number of Serial I/Os

Number of Timers

Number of External Interrupts

Barrel Shifter

Internal Bus Architecture

On Chip Data RAM Width

Number of DMA Channels

Length

Width